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ȸ - 74LS192 ̿ Up-Down Counter 2 / ȸ ǿ Դϴ. ̰ɷ ̹ ̻ ¾ҽϴ. ȭؿ! / 1. ȸε 2. ̷а 3. 4. м / |
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8p age   | 
3,000
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ȸ - 74LS192 ̿ Up-Down Counter 1 / ȸ ǿ Դϴ. ̰ɷ ̹ ̻ ¾ҽϴ. ȭؿ! / 1. ǥ 2. ̷ 3. Ʈ 4. PSpice ùķ̼ / 1. ǥ 7-segment 캸, Ѵ. 74LS192 캸, Ѵ. 74 |
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15p age   | 
3,000
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A+ ī(,COUNTER) ȸ / 12. ȸ 1. ȣ(Լ) ġ Ƿν κ 극 ᵵ BNC ڳ-ǾŬ ̺ JK flip-flop (HD74LS76AP) 2. ԷµǴ Ŭ ȸ̴. ⸦ ϴ ȸδ flip-flopε, N flip-fl |
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5p age   | 
800
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ȸ̴. ̴ Counter Ѵ. ⸦ flip-flop Ͽ (Count) Ѵ. N-bit Counter ʿ N flip-flop Ͽ ⸦ ϸ ȴ. (1) JK flip-flop JK flip-flop J, K Է 1 ° ȭ Ǿ µȴ. J, K 1 |
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5p age   | 
800
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VHDL ǽ(D-FF, JK-FF, Counter) / анVHDLǽ(D-FF,JK-FF,Counter) , Ʈġ, ùķ̼, ǥ Դϴ. D-FF Է CLK () () (ϰ) (ϰ) D 0 1 0 1 Q 0 1 D-FF CLK ۿϿ , Է ״ Ǵ ø÷̴. CLK ¿ϡ |
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9p age   | 
1,500
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VHDL ǽ(8bit Counter, State Machine) / анVHDL ǽ(8bit Counter, State Machine) 1. 8Bit Counter `Module` `Test Bench` `Simulation` `ǥ ` ClrN 0 1 1 . . . LdN X 0 1 . . . P X X 1 . . . T1 X X 1 . . . D1&D2 X D1&D2 D1&D2 . . . Q 00000000 D1&D2 D1&D2+1 . . . ̹ 8Ʈ īʹ 4Ʈ ī 2 ̡ |
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7p age   | 
1,500
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VHDL ǽ (D-FF, JK-FF, 8-bit counter) / анVHDL ǽ(D-FF, JK-FF, 8-bit counter) . D ø÷ D ø÷ Է ¿ ܼ ϴ ø÷ ߿ Ŭ CP Ǿ ȴٴ ̴. Է ϴ ٷ ٲ CP H` Ǵ ȴ. D ø÷ |
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5p age   | 
1,000
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ϸ ȴ. - Count Up Ripple Counter 켱 JK-F/F 7476 2 غѴ. ġ1 ù ° CLK ϰ ù ° CLK Q ٽ ° CLK Ѵ. 4° Ѵ. Ŭ ġ2 Ѵ. ȸθ ġ 1 HIGH ϰ ġ2 LOW |
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8p age   | 
1,800
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츮 ϴ ع̴. Counter electrode, Working electrode, Reference electrode̴. R.E(Reference electrode) Ǵ ̴. C.E(counter electrode) Pt ϸ W.E(working electrode) ITO-glass Ѵ. ITO-glass ǿ Indium Tin Oxide ̴. ̰ 1cm, 3cm ũ ߡ |
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4p age   | 
1,200
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ڿ (Register), ī(Counter) ִ. |
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14p age   | 
3,000
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ȸҰ |
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