반도체공정 Report-1

1. PIDS의 문제점

1) Scaling of MOSFETs to the 32nm technology generation

2) Implementation of high-k gate dielectric and metal gate electrode in a

3) Timely assurance for the reliability of multiple and rapid material, process, and structural changes

4) Scaling of DRAM and SRAM to the 32nm technology generation

5) Scaling high-density non-volatile memory(NVM) to the 32nm technology

6) Implementation of advanced, non-classical CMOS with enhanced drive current and acceptable control of short channel effects for highly scaled MOSFETs

7) Dealing with fluctuation and statistical process variations in sub-11 nm gate length MOSFETs

8) Identifying, selection, and implementing new memory structures

9) Identifying, selecting, and implementing novel interconnect schemes

10) Toward the end of the Roadmap or beyond, identification, selection, and implementation of advanced, beyond CMOS devices and architectures for advanced information processing

2. Memory Technology