|
| |
|
|
아주대 컴퓨터구조 기말 기말시험
파일 
아주대 컴퓨터구조 기말 기말시험.pdf
[Size :
82 Kbyte
]
아주대 컴퓨터구조 기말 기말시험.pdf
[Size :
82 Kbyte
]
분량 2 Page
가격 1,000 원
×
링크주소가 복사 되었습니다.
원하는 곳에 붙혀넣기 하세요
원하는 곳에 붙혀넣기 하세요
카트
|
다운받기
|
 네이버 ID로 다운 받기  카카오 ID로 다운 받기  구글 ID로 다운 받기  페이스북 ID로 다운 받기 |
뒤로
|
목차/차례
- Computer Architecture Final Exam
- 11.12.10 1. Assume we have PC=300, R1=500, XR=300, AC=700. And the memory contains. Fill the blanks. (2)
- Address 300 301 Content Load to AC Mode Address=500 Addressing mode Indirect address Relative 500 900 Indexed Register indirect 800 801 802 400 700 200 Effective address Content of AC
- Next instruction
- 900
- 800
- 2. A system has a cache block that uses the direct mapping and the LRU replacement policy. Show tag changes in the cache (2), the number of...
본문/내용
Computer Architecture Final Exam
11.12.10 1. Assume we have PC=300, R1=500, XR=300, AC=700. And the memory contains. Fill the blanks. (2)
Address 300 301 Content Load to AC Mode Address=500 Addressing mode Indirect address Relative 500 900 Indexed Register indirect 800 801 802 400 700 200 Effective address Content of AC
Next instruction
900
800
2. A system has a cache block that uses the direct mapping and the LRU replacement policy. Show tag changes in the cache (2), the number of cache hit (1) and their physical addresses (2). CPU address format is | 2-bit tag | 3-bit block | 1-bit word |
The sequence of referenced memory addresses is 04, 13, 05, 16, 17, 02, 13 in Hexa code.
3. About “segmented-page mapping”. Assume the size of page = the size of block. There are 3 bits for segment number in logical address, 2 bits for page number and 3 bits for word offset. The size of memory is 32 (address from 0 to 31). The memory is filled from top to bottom. 0, 1, 2, 3, 4, …
11.12.10 1. Assume we have PC=300, R1=500, XR=300, AC=700. And the memory contains. Fill the blanks. (2)
Address 300 301 Content Load to AC Mode Address=500 Addressing mode Indirect address Relative 500 900 Indexed Register indirect 800 801 802 400 700 200 Effective address Content of AC
Next instruction
900
800
2. A system has a cache block that uses the direct mapping and the LRU replacement policy. Show tag changes in the cache (2), the number of cache hit (1) and their physical addresses (2). CPU address format is | 2-bit tag | 3-bit block | 1-bit word |
The sequence of referenced memory addresses is 04, 13, 05, 16, 17, 02, 13 in Hexa code.
3. About “segmented-page mapping”. Assume the size of page = the size of block. There are 3 bits for segment number in logical address, 2 bits for page number and 3 bits for word offset. The size of memory is 32 (address from 0 to 31). The memory is filled from top to bottom. 0, 1, 2, 3, 4, …
| 📝 Regist Info |
|
I D : comm*** Date : 2017-04-03 FileNo : 17042073 |
Cart  | |
| |