하드웨어-소프트웨어 통합설계에서의 새로운 분할 방법

[1] Business Week, McGRAW-HILL, pp.59, April 25, 1994.
[2] W. Wolf, `Guest editor`s introduction : Hardware-Software Codesign,` IEEE Design and Test of Computers, p.5, Sep. 1993.
[3] K. Keutzer, `Hardware-software Co-design and ESDA,` Proc. of DAC, pp.435-436, June 1994.
[4] R. Gupta and G. De Micheli, `System-level Synthesis Using Reprogrammable Component,` Proc. of EDAC, pp.2-7, March 1992.
[5] R. Ernst, J. Henkel, and T. Benner, `Hardware-Software Cosynthesis for Microcontrollers,` IEEE Design and Test of Computers, Vol.10, pp.64-75, Dec. 1993.
[6] N. S. Woo, A. E. Dunlop, and W. Wolf, Codesign from cospecification, IEEE Computer, Jan. 1994.
[7] J. Buck, S. Ha, E. Lee, and D. Messerschmitt, `Ptolemy: a framework for simulating and prototyping heterogeneous systems,` International Journal of Computer Simulation, Vol.4, pp.155-182, April 1994.
[8] A. Kalavade and E. A. Lee, `A hardware-software codesign methodology for DSP applications,` IEEE Design and Test of Computers, Vol.10, No.3, pp.16-28, Sept. 1993.
[9] U. Washington, Scheduling by Bellman-Ford Single-source Longest Algorithm, IEEE Micro, pp.37-43, August 1994.
[10] W. H. Wong and R. Jain, `PARAS: System-Level Concurrent Partitioning and Scheduling,` Proc. of ICCAS, pp.440-445, 1995.
[11] R. K. Gupta, `Software Synthesis for Embedded Systems,` Proc. of ISCAS, pp.643-646, 1996.
[12] D. Park and H. Shin, `Partitioning for Minimal Memory in Hardware-Software Codesign,` Proc. of ISCAS, pp.647-650, May 1996.
[13] J. Henkel and R. Ernst, `A Hardware/Software Partitioner using a dynamically determined Granularity,` Proc. of DAC, pp.691-696, 1997.
[14] S. Bakshi and D. D. Gajski, `Hardware/Software Partitioning and Pipelining,` Proc. of DAC, pp.713-716, 1997.
[15] H. Shin and C. Kim, `A Simple Yet Effective Technique for Partitioning,` IEEE Trans. on VLSI Systems, Vol.1, No.3, pp.380-386, Sept. 1993.
[16] J. Henkel, T. Benner, and R. Ernst, `Hardware Generation and Partitioning Effects in the COSYMA System,` IEEE Int`l Workshop on Hardware/Software Codesign, pp.29-40, 1993.
[17] W. Ye, R. Ernst, T. Benner, and J. Henkel, `Fast Timing Analysis for Hardware-Software Co-synthesis,` Proc. of ICCAD, pp.452-457, 1993.
[18] M. McFarland, A. C. Parker, and Raul Camposano,` Tutorial on High-Level Synthesis,` Proc. of DAC, pp.330-336, 1988.
[19] B. Pangrle and D. D. Gajski, `Slicer : A State Synthesis for Intelligent Silicon Compilation,` Proc. of ICCAD, pp.42-45, 1987.
[20] A. C. Parker, T. Pizzaro and M. Mliner, `MAHA : A Program for Datapath Synthesis,` Proc. of DAC, pp.461-465, 1986.
[21] D. D. Gajski, A. Wu, N. Dutt, and S. Lin, High-level Synthesis : Introduction to chip and system design, Kluwer Academic Publishers, 1993.
[22] P. Paulin, J. Knight, nad E. Girczyn, `HAL : A Multiple Paradigm Approach to Automatic Data Path Synthesis,` Proc. of DAC, pp.263-270, 1986.
[23] C. Hwang, Y. Hsu, and Y. Lin, `Optimum and Heuristic Data Path Scheduling Under Resource Constraint,` Proc. of DAC, pp.65-70, 1990.
[24] R. Camposano and R. Bergamaschi, `Synthesis Using Path-based Scheduling : Algorithms and Exercises,` Proc. of DAC, pp.450-455, 1990.
[25] S. H. Huang, Y. L. Jeang, et. al., `A Tree-based Scheduling Algorithm for Control-dominated Circuits,` Proc. of DAC, pp.578-582, 1993.
[26] D. C. Ku and G. De Micheli, `Realtive Scheduling Under Timing Constraints,` Proc. of DAC, pp.59-64, 1990.
[27] A. P. Chandrakasan, M. Potkonjak, R. Mehra, J. M. Rabaey, and R. W. Brodersen, `Optimizing Power Using Transformations,` IEEE Trans. on CAD, Vol.14, pp.12-30, Jan. 1995.
[28] E. Musoll and J. Cortadella, `Scheduling and Resource Binding for Low Power,` Proc. Int`l Symposium on System Synthesis, pp.104-109, 1995.
[29] E. Musoll and J. Cortadella, `High-level Synthesis Technique for Reducing the Activity of Functional Units,` Proc. Int`l Symposium on Low Power Design, pp.99-104, 1995.
[30] D. Kim and K. Choi, `Power-conscious High Level Synthesis Using Loop Folding,` Proc. of DAC, pp.441-445, 1997.
[31] S. Y. Ohm, F. J. Kurdahi, and N. Dutt, `Comprehensive Lower Bound Estimation from Behavioral Descriptions,` Proc. of ICCAD, pp.182-187, 1994.
[32] H. Shin, `Advances in Hardware-Software Codesign Techniques,` Proc. of ICVC, pp.227-231, 1997.

[33] N. Kim and H. Shin, `New Partitioning Techniques in Hardware-Software Codesign,` Proc. of ICVC, pp.376-378, 1997.
[34] 신현철, 최기영, 김보관, 하순회, 하드웨어-소프트웨어 통합설계 기술 개발 결과보고서, 한국과학재단, 1997.
[35] D. W. Engels, `Periodic Scheduling in Polis Codesign Environment,` UCB/ERL M 95/101, Univ. of Calif., Berkeley, Dec. 1995.
[36] D. D. Gajski, F. Vahid, S. Narayan, and J. Gong, Specification and Design of Embedded Systems, Prentice Hall, pp.104-112, 1994.
[37] T. B. Ismail and A. A. Jerraya, Synthesis steps and design models for codesign, IEEE Computer, pp.44-52, Feb. 1995.
[38] K. Buchenrieder and J. Rozenbilt, Codesign : computer-aided software/hardware engineering, IEEE, 1995.
[39] A. Kalavade, `System-level Codesign of Mixed Hardware-Software Systems,` UCB/ERL M 95/88, Univ. of Calif., Berkeley, Oct. 1995.
[40] I. Karkovski and R. Otten, `An Automatic Hardware-Software Partitioner Based on the Possibilistic Programming, Proc. of EDAC, pp.473-479, 1996.
[41] G. De Micheli, Computer-aided Hardware-Software Codesign, IEEE Micro, pp.10-16, August 1994.
[42] R. Niemann and P. Marwedel, `Hardware/Software Partitioning using Integer Programming,` Proc. of EDAC, pp.473-479, 1996.
[43] J. K. Adams and D. E. Thomas, `The Design of Mixed Hardware/Software Systems,` Proc. of DAC, pp.515-520, 1996.
[44] G. Gong, D. Gajski, and S. Bakshi, `Model Refinement for Hardware-Software Codesign,` ACM Trans. on Design Automation of Electronic Systems, Vol.2, No.1, pp.22-41, Jan 1997.