[공학]논리회로 설계 - 디코더 인코어 보고서

1. 개 요

○ 가산기 설계를 통한 전반적인 Modelsim, Xilinx ISE 사용법 실습
○ TEST bench, simulation 방법 이해

2. 문 제

(1) 3*8 Decoder

-Behavioral modeling
library ieee;
use ieee.std_logic_1164.all;
entity decoder is
port (x : in std_logic_vector(2 downto 0);
d : out std_logic_vector(7 downto 0));
end decoder;
architecture behavioral of decoder is
begin
process (x)
begin
case x is
when 000 〓] d [〓 10000000 ;
when 001 〓] d [〓 xxx00000 ;
when xxx 〓] d [〓 0xxx0000 ;
when xxx 〓] d [〓 00xxx000 ;
when 100 〓] d [〓 000xxx00 ;
when 101 〓] d [〓 0000xxx0 ;
when 110 〓] d [〓 00000xxx ;
when others 〓] d [〓 00000001 ;
end case;
end process;
end behavioral;
-Data flow modeling
library ieee;
use ieee.std_logic_1164.all;
entity decoder_dataflow is
port(x: in s…(생략)

d(2) [〓 not x(0) and x(1) and not x(2);

d(3) [〓 x(0) and x(1) and not x(2);

d(4) [〓 not x(0) and not x(1) and x(2);

d(5) [〓 x(0) and not x(1) and x(2);

d(6) [〓 not x(0) and x(1) and x(2);

d(7) [〓 x(0) and x(1) and x(2);