verilog ���怨�[���吏���� ��쇰━ ���濡�]

紐⑤�� 諛� ���裕щ����댁��

1. 湲곕낯 ���怨� ������ (0.1珥�~1遺���⑥��, ��ㅽ�����移�)
<���泥� ���媛�紐⑤����댁��留� 1遺�源�吏�留� 肄���⑺�������듬�����.>
���湲곕낯 ���媛� 紐⑤��

`timescale 100ns/1ns

module timer_go
(c1k,reset,comma_a,sec_b,sec_a,min_b,min_a,hour_b,hour_a,night_a,c1k_b,c1k_c);

input c1k,reset;

output [5:0] comma_a, sec_b, min_b, hour_b;
output [4:0] sec_a, min_a;
output [2:0] hour_a;
output [3:0] night_a;
output c1k_c;
output [17:0] c1k_b;

reg [5:0] comma_a, sec_b, min_b, hour_b;
reg [4:0] sec_a, min_a;
reg [2:0] hour_a;
reg [3:0] night_a;
reg c1k_c;
reg [17:0] c1k_b;

initial
begin
comma_a=0;
sec_a = 0;
sec_b = 0;
min_a = 0;
min_b = 0;
hour_a = 0;
hour_b = 0;
night_a = 4`hA;
c1k_b = -1;
c1k_c = 0;

end

always @ (posedge c1k or posedge reset)

begin

if (c1k_b == 18`d99999)
begin
c1k_b <= 0;
c1k_c <= 1;
end
else
begin
c1k_b <= c1k_b + 1;
c1k_c = 0;
end
end

always @ (posedge c1k_c or pose���(������)