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VHDL¿¡ °üÇÏ¿©_1144367.hwp
 
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VHDL ÀϹÝÀûÀÎ ¸Þ´º¾óÀÔ´Ï´Ù.
VHDL¿¡°üÇÏ¿©
¸ñÂ÷/Â÷·Ê
1. Entity
2. Architecture
3. Component Instantiation
4. Configuration
5. Concurrent Statement
6. Sequential Statement
7. Delay Modeling
8. Operator
9. Block & Scope Rule
10. Attribute
º»¹®/³»¿ë
(4) Concurrent Assert¹®°ú Procedure Call
ÀÌ´Â º´Ç๮ ¼öÇà ȯ°æ¿¡¼ Assert¹®À» »ç¿ëÇϰųª Procedure Call À» »ç¿ëÇÏ´Â ¹æ¹ýÀ» ¸»ÇÑ´Ù.
ÀÌ»ó°ú °°Àº ¹®ÀåµéÀÌ º´Ç๮À̶ó ºÒ¸®¿ì´Â ÀÌÀ¯´Â ¹®ÀåÀÇ ¼ø¼¿¡ »ó °ü¾øÀÌ ¾î¶² À̺¥Æ®¿¡ µû¶ó ¹®ÀåÀÌ ½ÇÇàµÇ±â ¶§¹®À̸ç ÀÌ·± ¹®Àå Æ¯¼ºÀÌ H/W¸¦ ±â¼úÇϴµ¥ »ó´çÈ÷ ÀûÇÕÇϱ⠶§¹®¿¡ ¸¹ÀÌ »ç¿ëµÈ´Ù.
6. Sequential Statement
VHDL ¹®ÀåÀÇ ¶Ç´Ù¸¥ ±â¼ú ¹æ¹ýÀÎ Sequential Statement(¼øÂ÷¹®)Àº Process¹®À̳ª Subprogram ³»¿¡¼ »ç¿ëµÇ¸ç ¸» ±×´ë·Î À§¿¡¼ºÎÅÍ Â÷·Ê ´ë·Î ½ÇÇàµÇ´Â ¹®ÀåÀÌ´Ù. ¸ÕÀú Process¹®¿¡ ´ëÇØ »ìÆìº¸¸é Process¹®Àº sequential statement¸¦ »ç¿ëÇÒ¼ö ÀÖ´Â ÇϳªÀÇ µ¢¾î¸®·Î Àüü µ¢¾î¸® ÀÚü´Â ConcurrentÇÏ°Ô ½ÇÇàµÇÁö¸¸ ³»ºÎÀÇ ¹®ÀåµéÀº ¼øÂ÷ÀûÀ¸·Î ½ÇÇàµÈ´Ù. Áï Process¹®ÀÌ ¿©·¯°³°¡ ÀÖÀ» ¶§ °¢°¢ÀÇ Process¹®µéÀº º´ÇàÀûÀ¸·Î ½ÇÇàµÇÁö¸¸ ±× Process³»ºÎÀÇ ¹®ÀåµéÀº ¼øÂ÷ÀûÀ¸·Î ½ÇÇàµÈ´Ù´Â ¸»ÀÌ´Ù.
Process¹®ÀÇ ±¸Á¶´Â ´ÙÀ½°ú °°´Ù.
[process_·¹À̺í;]
process [(sensitivity_list)]
{¼±¾ð¹®}
begin
{sequential¹®}
end process [process_·¹À̺í];
process¼±¾ð ¿ìÃøÀÇ sensitivity_l¡¦(»ý·«)